[EI 502, IC 503, EI 405, EI 611] Ready & Hold Signal in a Microprocessor

This is a favorite question of mine and I have been able to stump a large number of interviewees during my corporate life.
Question: What is the difference in the ready and hold signals offered on microprocessors?

Answer: Let's deal with the hold signal related action first. Whenever bus masters other than the CPU needs to start transferring data to the memory, through the DMA action, it needs to drive the system bus. The DMA controller on the other bus master will have to drive the starting memory address from/to where data is to be transferred. It will control data and control buses to actually transfer the required amount of data. To be able to do this there should not be any other bus masters electrically. So when requested for the bus by another bus master, the CPU will acknowledge with a hold acknowledge signal ( HLDA in 8085, or something named similarly) after it tri-states the bus (makes the interface of the CPU with the bus in high impedance mode). The bus master can start driving the bus now and communicate with the memory system.

The ready signal on the other hand helps comparatively slower memory subsystem to communicate with the CPU read/write requests. The CPU is usually very fast. It communicates with the memory system synchronously, in sync with a system clock. Which means the CPU can set up address lines, puts out read or write signal after the addresses have stabilized. After a write signal, for example, the CPU samples the data lines after a fixed time, a multiple of the clock signal. Now, if the memory is not fast enough to put out data in that time, the CPU will read wrong data. To overcome this problem the memory device can request a delay by activating a signal named "Ready", the CPU will wait one clock cycle extra and then sample this line again. The CPU completes the cycle in the next clock cycle, when the ready signal is removed. So, this is a means of synchronization of memory and a master device. Yes, when a different bus master takes over the bus, similar problems may exist and is solved through the ready mechanism. This time the ready signal must go to the read/write controller of the DMA master operating the bus.